Buses are commonly used in computers and other electronic devices to send signals containing data from a driving (or generation) point to any number of receiving points. These busses can be created in printed circuit technology or from cables attached from one point to a second point. Backplane buses use circuit cards that plug in at regular intervals and represent loads along the bus. Cable busses employ cables with uniform electrical parameters that are connected at load devices in, for example, a daisy-chain fashion. Such a connection is used, for example, in Small Computers Systems Interface (SCSI) implementations.
The SCSI type of bus is also adaptable for use within backplane architectures. In systems of this type, the cable bus is replaced with a printed circuit board backplane. Intelligent peripheral devices, in the form of daughter boards, are then connected to the backplane connectors. The backplane architecture provides a compact and efficient method for connecting a series of intelligent peripheral devices to a computer system.
To work properly, a bus must maintain certain electrical characteristics. One of these characteristics is a controlled impedance. For an unloaded bus (i.e., a bus with no attached intelligent peripheral devices), the intrinsic impedance (Z.sub.0) can be calculated using the intrinsic impedance per unit length (L.sub.0) and the intrinsic capacitance per unit length (C.sub.0) in the following equation:
Z.sub.0=(L.sub.0/C.sub.0).sup.xc2xd
For a loaded bus, the preceding equation must be modified to reflect the effect of the attached load devices. This is most always in the form of added capacitance attributable to the attached load devices. Specifically, for a loaded bus the impedance (Zxe2x80x2) can be calculated by modifying the preceding equation to include the load capacitance per unit length (C.sub.d) resulting in the following equation:
Zxe2x80x2=(L.sub.0/(C.sub.0+C.sub.d)).sup.xc2xd
Based on this equation, it may be appreciated that increasing the load capacitance per unit length (C.sub.d) will result in decreasing values for the loaded impedance (Zxe2x80x2). Unfortunately, in backplane architectures, the buses are relatively short with each load device being separated by a relatively short distance. Since each load device adds capacitance to the bus, there is a tendency for backplane architectures to have relatively high values for load capacitance per unit length (C.sub.d). The result is that these architectures may be characterized by low intrinsic low values for impedance (Zxe2x80x2). Low values for impedance (Zxe2x80x2) results in a slow propagation speed for signals within the bus. This degrades the performance of the bus, making it more prone to operational errors and electrical noise.
To overcome the degrading effects of decreasing impedance, designers have been faced with a difficult compromise. One possible solution is to increase the length of the bus included in backplane architectures. Typically this is achieved by increasing the effective distance that each signal must travel between adjacent intelligent peripheral devices. Unfortunately, this requires that the size of the backplane be increased or that each signal path be routed in a tortuous pattern between adjacent load devices. The use of a tortuous pattern increases the difficulty of routing the signal paths within the backplane and may require that additional signals layers be added to the backplane. In either case, the cost of the backplane can be increased significantly. Another possible solution is to decrease the clock speed of the bus. Of course, this negatively impacts the performance of the bus, thereby making this solution generally unacceptable.
In addition to the problems discussed above, using RAMBUS technology, current computer data speeds may operate at 800 mega-transfers per second. As a result, the edge rates of the data pulses are on the order of 200 picoseconds or 0.2 nanoseconds. For high speed data ASIC comparisons distortions may occur due to reflections of the data signal from the terminating end of the data signal path. This path may include the path through the silicon itself Further the silicon path also has parasitic load that must be dealt with.
At these very high speeds (edge rates) the effect of otherwise small reactive components attached to electrical interconnects can have a very detrimental effect. The high speed edge rates of the Rambus-generated signals (e.g., in the Alpha EV7 that uses Rambus signals extensively) would cause significant signal reflections off of parasitic load points such as PWB routing vias or connector pins. Also, the transmission line electrical discontinuities caused by these physical discontinuities (like vias and connector pin metallization) would cause a noise margin reduction of these signals and possible logical failures.
Therefore there is now a need for a high speed bus or signal transmission line that has acceptable electrical signal impedance characteristics and operates at acceptable clock speeds.
The embodiments of the present invention address the aforementioned and related problems that are associated with a parasitic element. Since a discontinuity, such as a via, in a signal transmission line can introduce the parasitic element which affects the signal transmission, embodiments of the present invention provides a method and system directed to counteracting that transmission line parasitic element discontinuity.
More specifically, as embodied and broadly described herein, the system includes signal transmission line and a correction transmission line. The correction transmission line includes, based on the characteristics of the parasitic element, an inductance or a capacitance. The correction transmission line is positioned in the signal transmission line before or after the parasitic element.
In further accordance, as embodied and broadly described herein, one method includes determining a value of a parasitic element, be it a capacitive or an inductive parasitic element, that exists at a portion of a signal transmission line which has an impedance. This method also includes calculating a delay associated with a correction impedance of a correction transmission line that, based at least in part on the parasitic element value and the correction impedance of the correction transmission line, is operative to increase the signal transmission line impedance if the parasitic element is capacitive and to decrease the signal transmission line impedance if the parasitic element is inductive. This method further includes adding the correction transmission line to the portion of the signal transmission line at which the parasitic element exists.
In accordance with this method, the correction transmission line is divided equally and each half-part thereof is applied to the signal transmission line. Moreover, the half-parts of the correction transmission line are added one before and one after the parasitic element.
In another embodiment, a method enhances signal transmission characteristics of a signal transmission line. This method includes determining an intrinsic capacitance (or inductance) of a parasitic element that exists at a discontinuity portion of a signal transmission line which has an impedance. This method further includes calculating a delay associated with a correction impedance that, based at least in part on the intrinsic capacitance (or inductance) and the correction impedance, is operative to increase the signal transmission line impedance (or decrease the signal transmission line impedance if it is an intrinsic inductance of the parasitic element). Furthermore, this method includes adding the correction impedance to the signal transmission line so that one half of the calculated delay is added before and the other half of the calculated delay is added after the portion of the signal transmission line at which the parasitic element exists.
An advantage of a representative embodiment of the present invention is that it can eliminate the negative affects of parasitic element discontinuity within an electrical system.
Another advantage of a representative embodiment of the present invention is that it provides for the precise calculation of operating characteristics that are affected by capacitance cancellation.
Yet another advantage of a representative embodiment of the present invention is that it controls the impedance and cross talk levels in the ASCI design and incorporates features that cancel out the negative effects of the input capacitance of the silicon die.
Other advantages a representative embodiment of the present invention are that it enhances the manufacturing of electrical systems, is cost efficient, and is easy to implement.
Further advantages of embodiments of the present invention will be understood by those skilled in the art from the description herein. The advantages the embodiments of the invention will also be realized and attained from practice of the invention disclosed herein.